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[China]
Address: #506B, Henghui Business Center, No.77, Lingxia Nan Road, High Technology Zone, Huli, Xiamen 361006, China
Contact name:
XIAMEN POWERWAY ADVANCED MATERIAL CO., LTD. |
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12 Inch Silicon Wafer FZ N Type Phosphorus Doped Orientation 100 Prime Grade 12"
PAM-XIAMEN develops advanced crystal growth and epitaxy technologies, range from the silicon substrate to compound semiconductor, PAM-XIAMEN offer semiconductor silicon substrate with diameters from 1’’ (25.4 mm) to 12’’ (300 mm). We work either Cz (Czochralski) or FZ (Float Zone) silicon substrate. The polishing process is also made according to SEMI standard( the Semiconductor Equipment and Materials International standards). We also work ultra thin wafer, silicon oxide wafer SiO2 thin film, silicon nitride wafer Si3N4 thin film, metallization on silicon substrate, and epi wafer service.
12inch Silicon Wafer FZ N Type Phosphorus Doped Orientation 100 Prime Grade 12"
| Type | Conduction Type | Orientation | Diameter(mm) | Resistivity(Ω•cm) |
| High resistance | N&P | <100>&<111> | 50 - 300 | >1000 |
| NTD | N | <100>&<111> | 50 - 300 | 30-800 |
| CFZ | N&P | <100>&<111> | 50 - 300 | 1-50 |
| GD | N&P | <100>&<111> | 50 - 300 | 0.001-300 |
| Parameter | Unit | Value |
| Crystalline structure | - | Monocrystalline |
| Growth technique | - | FZ |
| Crystal Orientation | - | 100±0.5° |
| Conductance type | - | N |
| Dopant | - | Phosphorus |
| Diameter | mm | 300±0.2 mm |
| Resistivity | Ω/cm2 | 8000-14000Ωcm |
| Thickness | um | 650±5µm |
| TTV | um | ≤15 um |
| BOW | um | ≤35 um |
| Warp | um | ≤35 um |
| Site Flatness SFQD | um | 20X20mm: 0.40um |
| Surface Metals (Al,Ca,Cu,Fe,Ni,Zn,Cr,Na) | Atoms/cm2 | Max 5E10/cm2 |
| (G)STIR | um | Customer standard |
| Site Flatness-STIR | um | Customer standard |
| Metrology edge exclusion (lpd’s, mechanical parameters) | mm | 3 |
| LPD's | - | LPDs >= 0,30 µm (including COP’s) <=25 LPDs >= 0,20 µm (including COP’s) <=30 LPDs >= 0,16 µm (including COP’s) <=60 |
| Oxygen Concentration | ppma | 11-15 PPMA |
| Carbon Concentration | ppma | <1E16/cc |
| RRG | - | ≤15% |
| Front Surface | - | Polished |
| Back Surface | - | Polished |
| Edge Surface Condition | SEMI STD or Customer Request | |
| Notch | - | SEMI STD |
| Laser mark | - | SEMI STD or Customer Request |
| Packaging | Packaged in a class 100 clean room environment, Heat-sealed plastic inner/aluminium foil outer bags, Vacuum Packing | |
| If specific requirement by customer, will adjust accordingly | ||
| Parameter | Unit | Value |
How is Silicon Wafer Made?
Growth of Silicon Ingot: single crystal silicon wafers grow via the Czochralski (CZ) and FZ method,CZ ingot growth requires chunks of virgin polycrystalline silicon, depending on the dopant, the ingot becomes a P or N type ingot (boron: P type; Phosphorus, antimony, arsenic: N type).
Slicing:Once the ingot is fully-grown, it is ground to a rough size diameter that is slightly larger than the target diameter of the final silicon wafer. The ingot has a notch or flat cut into it, the ingot proceeds to slicing. The diamond edge saw helps to minimize damage to the wafers, thickness variation, and bow and warp defects.
After the wafers have been sliced, the lapping process begins.
Cleaning:The final and most crucial step in the manufacturing process is polishing the wafer. This process takes place in a clean room. Clean rooms have a rating system that ranges from Class 1 to Class 10,000. These particles are not visible to the naked eye and in an uncontrolled atmosphere, the workers must wear clean room suits that cover their body from head to toe and do not collect or carry any particles.
Polishing:Most prime grade silicon wafers go through 2-3 stages of polishing, using progressively finer slurries or polishing compounds. The polishing process occurs in two steps, which are stock removal and final chemical mechanical polish (CMP). Both processes use polishing pads and polishing slurry. The stock removal process removes a very thin layer of silicon and is necessary to produce a wafer surface that is damage-free. After polishing, the silicon wafers proceed to a final cleaning stage that uses a long series of clean baths. This process removes surface particles, trace metals, and residues. Oftentimes a backside scrub is done to remove even the smallest particles.
Packaging:Once the wafers complete the final cleaning step, engineers sort them by specification and inspect them under high intensity lights or laser-scanning systems. This detects unwanted particles or other defects that may have occurred during fabrication. All wafers that meet the proper specifications are packaged in cassettes and sealed with tape. The wafers ship in a vacuum-sealed plastic bag with an airtight foil outer bag. This ensures that no particles or moisture enters the cassette upon leaving the clean room.
Are You Looking for an Silicon Wafer?
PAM-XIAMEN is your go-to place for semiconductor wafers, including Silicon wafers, as we have been doing it for almost 30 years! Send us enquiry to learn more about the wafers that we offer and how we can help you with your next project. Our group team can give you technology support. send us email at sales@powerwaywafer.com or powerwaymaterial@gmail.com
