Active Member
|
[China]
Address: R1811, B Bldg, Jiahe Tower, No.3006 Shennan Mid Rd, Shenzhen, China
Contact name:CXDA-FPGA
CHUANGXINDA ELECTRONICS-TECH CO., LIMITED |
|
|
XC4VLX40-11FF668I Xilinx FPGA Chip FBGA-668 448 I/O Virtex-4
| Product Attribute | Attribute Value |
|---|---|
| Xilinx | |
| FPGA - Field Programmable Gate Array | |
| Virtex-4 | |
| 41472 | |
| 448 I/O | |
| 1.2 V | |
| - 40 C | |
| + 100 C | |
| SMD/SMT | |
| FBGA-668 | |
| Series: | XC4VLX40 |
| Brand: | Xilinx |
| Distributed RAM: | 288 kbit |
| Embedded Block RAM - EBR: | 1728 kbit |
| Maximum Operating Frequency: | 500 MHz |
| Moisture Sensitive: | Yes |
| Product Type: | FPGA - Field Programmable Gate Array |
| Factory Pack Quantity: | 1 |
| Subcategory: | Programmable Logic ICs |
| Tradename: | Virtex |
Summary of Virtex-4 FPGA Features
• Programmable single-ended or differential (LVDS) operation
• Input block with an optional single data rate (SDR) or double
data rate (DDR) register
• Output block with an optional SDR or DDR register
• Bidirectional block
• Per-bit deskew circuitry
• Dedicated I/O and regional clocking resources
• Built in data serializer/deserializer
• XtremeDSP™ Slice
- 18 x 18, two’s complement, signed Multiplier
- Optional pipeline stages
- Built-in Accumulator (48-bit) and Adder/Subtracter
• SelectIO™ Technology
- 1.5V to 3.3V I/O operation
- Built-in ChipSync™ source-synchronous technology
- Digitally controlled impedance (DCI) active termination
- Fine grained I/O banking (configuration in one bank)
The IOB registers are either edge-triggered D-type flip-flops or
level-sensitive latches.
IOBs support the following single-ended standards:
• LVTTL
• LVCMOS (3.3V, 2.5V, 1.8V, and 1.5V)
• PCI (33 and 66 MHz)
• PCI-X
• GTL and GTLP
• HSTL 1.5V and 1.8V (Class I, II, III, and IV)
• SSTL 1.8V and 2.5V (Class I and II)
