EP2AGZ300FF35I4N 554 I/O 11920 LABs ALTERA FPGA Chip

Arria II GX devices have dedicated configuration banks at Bank 3C and 8C, which support dedicated configuration pins and some of the dual-purpose pins with a
configuration scheme at 1.8, 2.5, 3.0, and 3.3 V. For Arria II GZ devices, the dedicated configuration pins are located in Bank 1A and Bank 1C. However, these
banks are not dedicated configuration banks; therefore, user I/O pins are available in Bank 1A and Bank 1C.

Dedicated VCCIO, VREF, and VCCPD pin per I/O bank to allow voltage-referenced I/O standards. Each I/O bank can operate at independent VCCIO, VREF, and
VCCPD levels.

Auto-Calibrating External Memory Interfaces
■ I/O structure enhanced to provide flexible and cost-effective support for different types of memory interfaces
■ Contains features such as OCT and DQ/DQS pin groupings to enable rapid and robust implementation of different memory standards
■ An auto-calibrating megafunction is available in the Quartus II software for DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, RLDRAM II memory interface
PHYs; the megafunction takes advantage of the PLL dynamic reconfiguration feature to calibrate based on the changes of process, voltage, and temperature (PVT).