Active Member
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[China]
Address: R1811, B Bldg, Jiahe Tower, No.3006 Shennan Mid Rd, Shenzhen, China
Contact name:CXDA-FPGA
CHUANGXINDA ELECTRONICS-TECH CO., LIMITED |
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EP2S60F1020I4N ALTERA FPGA Chip FBGA-1020 718 I/O Stratix II
| Product Attribute | Attribute Value |
|---|---|
| Intel | |
| FPGA - Field Programmable Gate Array | |
| Stratix II | |
| 60440 | |
| 3022 | |
| 718 I/O | |
| 1.2 V | |
| - 40 C | |
| + 85 C | |
| SMD/SMT | |
| FBGA-1020 | |
| Tray | |
| Series: | Stratix II EP2S60 |
| Brand: | Intel / Altera |
| Moisture Sensitive: | Yes |
| Operating Supply Current: | 500 mA |
| Product Type: | FPGA - Field Programmable Gate Array |
| Factory Pack Quantity: | 24 |
| Subcategory: | Programmable Logic ICs |
| Total Memory: | 2544192 bit |
| Tradename: | Stratix II |
| Part # Aliases: | 973068 |
Stratix® II devices contain a two-dimensional row- and column-based
architecture to implement custom logic. A series of column and row
interconnects of varying length and speed provides signal
interconnects between logic array blocks (LABs), memory block
structures (M512 RAM,
M4K RAM, and M-RAM blocks), and digital signal processing (DSP)
blocks.
Each LAB consists of eight adaptive logic modules (ALMs). An ALM is
the Stratix II device family’s basic building block of logic
providing
efficient implementation of user logic functions. LABs are grouped
into rows and columns across the device.
M512 RAM blocks are simple dual-port memory blocks with 512 bits
plus parity (576 bits). These blocks provide dedicated simple
dual-port or
single-port memory up to 18-bits wide at up to 500 MHz. M512 blocks
are grouped into columns across the device in between certain LABs.
