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Original Integrated Circuit Chip in Electronics 93LC66A-I/SN 1K-16K
Microwire
93LC66A-I/SN
1K-16K Microwire Compatible Serial EEPROMs
Feature
• Densities from 1 Kbits through 16 Kbits
• Low-power CMOS technology
• Available with or without ORG function: With ORG function: - ORG
pin at Logic Low: 8-bit word - ORG pin at Logic High: 16-bit word
Without ORG function: - ‘A’ version: 8-bit word - ‘B’ version:
16-bit word
• Program Enable pin: - Write-protect for entire array (93XX76C and
93XX86C only)
• Self-timed Erase/Write cycles (including auto-erase)
• Automatic ERAL before WRAL
• Power-on/off data protection circuitry
• Industry standard 3-wire serial I/O
• Device Status signal (Ready/Busy)
• Sequential Read function
• 1,000,000 E/W cycles
• Data retention > 200 years
• Pb-free and RoHS compliant
• Temperature ranges supported
- Industrial (I) -40°C to +85°C
- Automotive (E) -40°C to +125°C
Description:
Microchip Technology Inc. supports the 3-wire Microwire bus with
low-voltage serial Electrically Erasable PROMs (EEPROM) that range
in density from 1 Kbits up to 16 Kbits. Each density is available
with and without the ORG functionality, and selected by the part
number ordered. Advanced CMOS technology makes these devices ideal
for low-power, nonvolatile memory applications. The entire series
of Microwire devices are available in the standard 8-lead PDIP and
SOIC packages, as well as the more advanced packaging such as the
8-lead MSOP, 8-lead TSSOP, 6-lead SOT-23, and 8-lead DFN (2x3). All
packages are Pb-free. Pin Diagrams (not to scale)
Pin Function Table
| NAME | FUNCTION |
| CS | Chip Select |
| CLK | Serial Data Clock |
| DL | Serial Data Input |
| DO | Serial Data Output |
| VSS | Ground |
| PE | Program Enable |
| ORG | Memory Configuration |
| VCC | Power Supply |
Note: ORG and PE functionality not available in all products
DC CHARACTERISTICS
| All parameters apply over the specified ranges unless otherwise noted. | VCC = 1.8V to 5.5V Industrial | |||||
| Param. No. | Symbol | Parameter | Min. | Max. | Units | Conditions |
| A1 | FCLK | Clock frequency | —— | 3 2 1 | MHz MHz MHz | 4.5V ≤ VCC < 5.5V |
| A2 | TCKH | Clock high time | 200 250 450 | —— | ns ns ns | 4.5V ≤ VCC < 5.5V |
| A3 | TCKL | Clock low time | 100 200 450 | —— | ns ns ns | 4.5V ≤ VCC < 5.5V |
| A4 | TCSS | Chip Select setup time | 50 100 250 | —— | ns ns ns | 4.5V ≤ VCC < 5.5V |
| A5 | TCSH | Chip Select hold time | 0 | —— | ns | 1.8V ≤ VCC < 5.5V |
| A6 | TCSL | Chip Select low time | 250 | —— | ns | 1.8V ≤ VCC < 5.5V |
| A7 | TDIS | Data input setup time | 50 100 250 | —— | ns ns ns | 4.5V ≤ VCC < 5.5V |
| A8 | TDIH | Data input hold time | 50 100 250 | —— | ns ns ns | 4.5V ≤ VCC < 5.5V |
| A9 | TPD | Data output delay time | —— | 100 | ns | 4.5V ≤ VCC < 5.5V, |
| A10 | TCZ | Data output disable time | —— | 200 250 400 | ns ns ns | 4.5V ≤ VCC < 5.5V 2.5V ≤ VCC < 4.5V 1.8V ≤ VCC < 2.5V |
| A11 | TSV | Status valid time | —— | 200 300 500 | ns ns ns | 4.5V ≤ VCC < 5.5V 2.5V ≤ VCC < 4.5V 1.8V ≤ VCC < 2.5V |
| A12 | Twc | Program cycle time | —— —— —— | 5 6 2 | ms ms ms | Erase/Write mode 93XX76X/86X (AA and LC versions) 93XX46X/56X/66X (AA and LC versions) 93C46X/56X/66X/76X/86X |
| A13 | Twc | |||||
| A14 | TEC | Program cycle time | —— | 6 | ms | ERAL mode, 4.5V ≤ VCC ≤ 5.5V |
| A15 | Twl | —— | 15 | ms | WRAL mode, 4.5V ≤ VCC ≤ 5.5V | |
| A16 | —— | Endurance | 1M | —— | cycles | 25°C, VCC = 5.0V, (Note 2) |
Note
1: This parameter is periodically sampled and not 100% tested
2: ORG and PE pins not available on ‘A’ or ‘B’ versions.
3: Ready/Busy status must be cleared from DO, see Section 4.4 “Data
Out (DO)”.
