DS90UB948TNKDRQ1 UART Interface IC Serdes 1080p Dual FPD- Link III Deserializr

DS90UB948TNKDRQ1 UART Interface IC Serdes 1080p Dual FPD- Link III Deserializr

1 Features

• Qualified for Automotive Applications

• AEC-Q100 Qualified With the Following Results:

– Device Temperature Grade 2: –40°C to +105°C Ambient Operating Temperature

• Supports Pixel Clock Frequency up to 192 MHz for up to 2K (2048x1080) Resolutions With 24-Bit Color Depth

• 1-Lane or 2-Lane FPD-Link III Interface With De- Skew Capability

• Single or Dual OpenLDI (LVDS) Transmitter

  • – Single Channel: Up to 96-MHz Pixel Clock

  • – Dual Channel: Up to 192-MHz Pixel Clock

  • – Configurable 18-Bit RGB or 24-Bit RGB

• Four High-Speed GPIOs (up to 2 Mbps each)

• Adaptive Receive Equalization

  • – Compensates for Channel Insertion Loss of up to –15.3 dB at 1.7 GHz

  • – Provides Automatic Temperature and Cable Aging Compensation

• SPI Control Interfaces up to 3.3 Mbps

• I2C (Master/Slave) With 1-Mbps Fast-Mode Plus

• Image Enhancement (White Balance and Dithering)

• Supports 7.1 Multiple I2S (4 Data) Channels

   

2 Applications

• Automotive Infotainment:

• – Central Information Displays

• – Rear Seat Entertainment Systems

• – Digital Instrument Clusters

3 Description

The DS90UB948-Q1 is a FPD-Link III deserializer which, in conjunction with the DS90UB949A/949/947- Q1 serializers, converts 1-lane or 2-lane FPD-Link III streams into a FPD-Link (OpenLDI) interface. The Deserializer is capable of operating over cost- effective 50-Ω single-ended coaxial or 100-Ω differential shielded twisted-pair (STP) cables. It recovers the data from one or two FPD-Link III serial streams and translates it into dual pixel FPD-Link (8 LVDS data lanes + clock) supporting video resolutions up to 2K (2048x1080) with 24-bit color depth. This provides a bridge between HDMI enabled sources such as GPUs to connect to existing LVDS displays or application processors.

The FPD-Link III interface supports video and audio data transmission and full duplex control, including I2C and SPI communication, over the same differential link. Consolidation of video data and control over two differential pairs decreases the interconnect size and weight and simplifies system design. EMI is minimized by the use of low voltage differential signaling, data scrambling, and randomization. In backward compatible mode, the device supports up to WXGA and 720p resolutions with 24-bit color depth over a single differential link.

The device automatically senses the FPD-Link III channels and supplies a clock alignment and de-skew functionality without the need for any special training patterns. This ensures skew phase tolerance from mismatches in interconnect wires such as PCB trace routing, cable pair-to-pair leCM GROUPh differences, and connector imbalances.

Device Information