PCI9656-BA66BIG Integrated Circuit Chip 64-bit, 66MHz PCI Bus Mastering I/O Accelerator

PCI 9656

64-bit, 66MHz PCI Bus Mastering I/O Accelerator for Motorola PowerQUICC™ & Generic 32-bit, 66MHz Local Bus Designs

Connectivity

■ 64-bit, 66MHz PCI r2.2 compliant

■ Motorola PowerQUICC and generic 32-bit, 66MHz local bus modes

■ 3.3V I/O, 5V tolerant bus interfaces

■ PICMG 2.1 r2.0 Hot Swap Silicon

■ 272-ball, 27 x 27 mm, 1.27 mm pitch PBGA

Performance

■ Zero wait state burst operation

  – PCI bus bursts to 528 MB/sec

  – Local bus bursts to 264 MB/sec

■ 2 DMA Channels

  – Block and Scatter/Gather transfers

  – DMA descriptor ring management

  – Demand Mode and EOT Hardware controls

■ Direct Master data transfers

  – Generate any PCI transaction

  – Read ahead and programmable read prefetch counter

■ Direct Slave data transfers

  – Access 8-, 16-, and 32-bit local bus devices

  – Deferred reads, deferred writes, read ahead, posted writes, programmable read prefetch counter

Control

■ I ₂O r1.5 messaging unit

■ Eight mailbox and two doorbell registers

■ PCI arbiter supports 7 external masters

■ Host mode reset/interrupt signal configuration

■ PCI D3_COLD Power Management Event (PME) generation support

■ Serial EEPROM interface

■ JTAG boundary scan

Maximum PCI Bandwidth for Your 32-bit Local Bus Applications

The PCI 9656 offers flexible connectivity and high performance I/O acceleration features to enable leading edge PCI, CompactPCI, and embedded host designs.

Motorola® MPC 850/860 PowerQUICC Designs

The PCI 9656 is the perfect match for the industry leading 32-bit communication processor, the Motorola MPC 850/860 PowerQUICC. The PCI 9656 provides a direct connection to PowerQUICC devices, enabling high-speed 64-bit, 66MHz PCI performance with its Data Pipe Architecture™ technology.

Generic 32-bit, 66MHz Local Bus Designs

The PCI 9656 provides direct connection to two generic industry standard interconnect buses. Designers use these 32-bit, 66MHz buses for a myriad of high-speed devices ranging from processors, to DSPs, to memories, to custom ASICs and FPGAs. The PCI 9656 Data Pipe Architecture technology enables high-speed, 64-bit, 66MHz PCI I/O with those devices

Move Your 32-bit Local Bus Designs Up to 64-bit, 66MHz PCI Operation

As PCI evolves to meet the ever increasing I/O demands of leading edge systems, PLX continues to provide leading edge, high performance PCI I/O acceleration solutions. Based on the architecture of the industry-leading PCI 9054, the PCI 9656 offers a variety of enhancements for the needs of today's telecom, networking, and I/O adapter designs:

■ 64-bit, 66MHz PCI operation

■ 32-bit, 66MHz local bus operation

■ Dynamic DMA descriptor ring management with Valid bit semaphore control

■ PICMG 2.1 r2.0 Hot Swap Silicon, including Bias Voltage, Early Power, 64-bit Initialization, and Intially Not Responding Support

■ PCI Power Management r1.1 D3COLD Power Management Event (PME) generation

■ PCI arbiter supporting 7 external masters

■ Reset and interrupt pins configurable for embedded host applications

■ JTAG boundary scan

The PCI 9656 is register compatible with the PCI 9054, enabling easy software migration.

PCI 9656 Features

The PCI 9656 64-bit, 66MHz PCI I/O accelerator is the most advanced, general-purpose bus mastering device available for Motorola MPC 850/860 PowerQUICC and generic 32-bit, 66MHz local bus based designs. The PCI 9656 incorporates PLX’s industry leading Data Pipe Architecture technology, featuring DMA engines, programmable Direct Master and Direct Slave data transfer modes, and PCI messaging functions.

PCI 9656 PowerQUICC CompactPCI Adapter

PCI 9656 Internal Block Diagram