Shenzhen Sai Collie Technology Co., Ltd. |
|
S9S12G128F0MLL MCU Microcontroller Unit 16-Bit 25MHz FLASH Memory Package 100-LQFP
Core Size | ||
Speed | 25MHz | |
Connectivity | CANbus, IrDA, LINbus, SCI, SPI | |
Peripherals | LVD, POR, PWM, WDT | |
Number of I/O | 86 | |
Program Memory Size | ||
Program Memory Type | FLASH | |
EEPROM Size | 4K x 8 | |
RAM Size | 8K x 8 | |
Voltage - Supply (Vcc/Vdd) | 3.13V ~ 5.5V | |
Data Converters | A/D 12x10b | |
Oscillator Type | Internal | |
Operating Temperature | -40°C ~ 125°C (TA) | |
Mounting Type | Surface Mount | |
Package / Case | 100-LQFP | |
Supplier Device Package | 100-LQFP (14x14) |
General description:
The LPC5411x are ARM Cortex-M4 based microcontrollers for embedded
applications. These devices include an ARM Cortex-M0+ coprocessor,
up to 192 KB of on-chip SRAM, up to 256 KB on-chip flash,
full-speed USB device interface with Crystal-less operation, a DMIC
subsystem with PDM microphone interface and I2S, five
general-purpose timers, one SCTimer/PWM, one RTC/alarm timer, one
24-bit Multi-Rate Timer (MRT), a
Windowed Watchdog Timer (WWDT), eight flexible serial communication
peripherals (each of which can be a USART, SPI, or I2C interface),
and one 12-bit 5.0 Msamples/sec ADC, and a temperature sensor. The
ARM Cortex-M4 is a 32-bit core that offers system enhancements such
as low power consumption, enhanced debug features, and a high level
of support block integration. The ARM Cortex-M4 CPU incorporates a
3-stage pipeline, uses a Harvard architecture with separate local
instruction and data buses as well as a third bus for peripherals,
and includes an internal prefetch unit that supports speculative
branching. The ARM Cortex-M4 supports single-cycle digital signal
processing and SIMD instructions. A hardware floating-point unit is
integrated in the core.
The ARM Cortex-M0+ coprocessor is an energy-efficient and
easy-to-use 32-bit core which is code and tool-compatible with the
Cortex-M4 core. The Cortex-M0+ coprocessor offers up to 150 MHz
performance with a simple instruction set and reduced code size.