FPGA Programmable IC Chips XC3S1000-4FGG456C 1000000 System Gate 1.2v

Programmable Integrated Circuit XC3S1000-4FGG456C 1000000 System Gate 1.2v FPGA

Applications

• Automotive driver assistance, driver information, and infotainment
• Broadcast camera
• Industrial motor control, industrial networking, and machine vision
• IP and Smart camera
• LTE radio and baseband
• Medical diagnostics and imaging
• Multifunction printers

• Video and night vision equipment

Specifications

Description

The Spartan®-3 family of Field-Programmable Gate Arrays is specifically designed to meet the needs of high volume, cost-sensitive consumer electronic applications. The eight-member family offers densities ranging from 50,000 to 5,000,000 system gates, as shown in Table 1.

The Spartan-3 family builds on the success of the earlier Spartan-IIE family by increasing the amount of logic resources, the capacity of internal RAM, the total number of I/Os, and the overall level of performance as well as by improving clock management functions. Numerous enhancements derive from the Virtex®-II platform technology. These Spartan-3 FPGA enhancements, combined with advanced process technology, deliver more functionality and bandwidth per dollar than was previously possible, setting new standards in the programmable logic industry.

Because of their exceptionally low cost, Spartan-3 FPGAs are ideally suited to a wide range of consumer electronics applications, including broadband access, home networking, display/projection and digital television equipment.

The Spartan-3 family is a superior alternative to mask programmed . FPGAs avoid the high initial cost, the lengthy development cycles, and the inherent inflexibility of conventional ASIC. Also, FPGA programmability permits design upgrades in the field with no hardware replacement necessary, an impossibility with 

Features

Low-cost, high-performance logic solution for high-volume, consumer-oriented applications

• Densities up to 74,880 logic cells

• SelectIO™ interface signaling

• Up to 633 I/O pins

• 622+ Mb/s data transfer rate per I/O

• 18 single-ended signal standards

• 8 differential I/O standards including LVDS, RSDS

• Termination by Digitally Controlled Impedance

• Signal swing ranging from 1.14V to 3.465V

• Double Data Rate (DDR) support

• DDR, DDR2 SDRAM support up to 333 Mb/s

• Logic resources

• Abundant logic cells with shift register capability

• Wide, fast multiplexers

• Fast look-ahead carry logic

• Dedicated 18 x 18 multipliers

• JTAG logic compatible with IEEE 1149.1/1532

• SelectRAM hierarchical memory

• Up to 1,872 Kbits of total block RAM

• Up to 520 Kbits of total distributed RAM

• Digital Clock Manager (up to four DCMs)

• Clock skew elimination

• Frequency synthesis

• High resolution phase shifting

• Eight global clock lines and abundant routing

• Fully supported by Xilinx ISE  and WebPACK software development systems

• MicroBlaze and PicoBlaz  processor, PCI, PCI Express PIPE Endpoint, and other IP cores

• Pb-free packaging options

• Automotive Spartan-3 XA Family variant

Package Marking

Figure 2 shows the top marking for Spartan-3 FPGAs in the quad-flat packages. Figure 3 shows the top marking for Spartan-3 FPGAs in BGA packages except the 132-ball chip-scale package (CP132 and CPG132). The markings for the BGA packages are nearly identical to those for the quad-flat packages, except that the marking is rotated with respect to the ball A1 indicator. Figure 4 shows the top marking for Spartan-3 FPGAs in the CP132 and CPG132 packages. The “5C” and “4I” part combinations may be dual marked as “5C/4I”. Devices with the dual mark can be used as either -5C or -4I devices. Devices with a single mark are only guaranteed for the marked speed grade and temperature range. Some specifications vary according to mask revision. Mask revision E devices are errata-free. All shipments since 2006 have been mask revision E.

Trading Guide                                                                               

Field Programmable Gate Array XC7A35T-2FGG484I