ChongMing Group (HK) Int'l Co., Ltd |
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SN74LVC1G123DCUR Programmable Logic ICS Trgrable Mnstbl Mltvbrtrw/SchmttTrgr
1 Features
Supports 5-V VCC Operation
Inputs Accept Voltages to 5.5 V
Maxtpd of8nsat3.3V
Supports Mixed-Mode Voltage Operation on All Ports
Supports Down Translation to VCC
Schmitt-Trigger Circuitry on A and B Inputs for Slow Input Transition Rates
Edge Triggered From Active-High or Active-Low Gated Logic Inputs
Retriggerable for Very Long Output Pulses, Up to 100% Duty Cycle
Overriding Clear Terminates Output Pulse
Glitch-Free Power-Up Reset on Outputs
Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
2 Applications
AV Receivers
Blu-ray Players and Home Theaters
DVD Recorders and Players
Desktop PCs or Notebook PCs
Digital Radio and Internet Radio Players
Digital Video Cameras (DVC) A
Embedded PCs
GPS: Personal Navigation Devices
Mobile Internet Devices CLR
Network Attached Storage (NAS)
Personal Digital Assistant (PDA)
Server PSU
Solid-State Drive (SSD): Client and Enterprise
Video Analytics Servers
Wireless Headsets, Keyboards, and Mice
3 Description
The SN74LVC1G123 device is a single retriggerable monostable multivibrator designed for 1.65-V to 5.5-V VCC operation.
This monostable multivibrator features output pulse- duration control by three methods. In the first method, the A input is low, and the B input goes high. In the second method, the B input is high, and the A input goes low. In the third method, the A input is low, the B input is high, and the clear (CLR) input goes high.
The output pulse duration is programmed by selecting external resistance and capacitance values. The external timing capacitor must be connected between Cext and Rext/Cext (positive) and an external resistor connected between Rext/Cext and VCC. To obtain variable pulse durations, connect an external variable resistance between Rext/Cext and VCC. The output pulse duration also can be reduced by taking CLR low.
Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input pulse. The A and B inputs have Schmitt triggers with sufficient hysteresis to handle slow input transition rates with jitter-free triggering at the outputs.
Device Information
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
SN74LVC1G123 | SSOP (8) | 2.95 mm × 2.80 mm |
VSSOP (8) | 2.30 mm × 2.00 mm | |
DSBGA (8) | 1.91 mm × 0.91 mm |