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DRAM Memory Chip DRAM Memory Chip H9HCNNNBUUMLHR 16Gb LPDDR4 BGA200 Memory Chip Storage
Specifications
Features
· VDD1 = 1.8V (1.7V to 1.95V)
· VDD2, VDDCA and VDDQ = 1.1V (1.06 to 1.17)
· VSSQ terminated DQ signals (DQ, DQS_t, DQS_c, DMI)
· Single data rate architecture for command and address;
- all control and address latched at rising edge of the clock
· Double data rate architecture for data Bus;
- two data accesses per clock cycle
· Differential clock inputs (CK_t, CK_c)
· Bi-directional differential data strobe (DQS_t, DQS_c)
- Source synchronous data transaction aligned to bi-directional
differential data strobe (DQS_t, DQS_c)
· DMI pin support for write data masking and DBIdc functionality
· Programmable RL (Read Latency) and WL (Write Latency)
· Burst length: 16 (default), 32 and On-the-fly
- On the fly mode is enabled by MRS
· Auto refresh and self refresh supported
· All bank auto refresh and directed per bank auto refresh
supported
· Auto TCSR (Temperature Compensated Self Refresh)
· PASR (Partial Array Self Refresh) by Bank Mask and Segment Mask
· Background ZQ Calibration
| Part No.
| Den.
| Org.
| Vol
| Speed
| Power
| PKG
| Product Status
|
|---|---|---|---|---|---|---|---|
| H9HCNNNBUUMLHR | 16Gb | x16 | 1.8V-1.1V-1.1V | L | Low Power | 200 | Mass production |
| H9HKNNNBTUMUAR | 16Gb | x16 | 1.8V-1.1V-1.1V | L | Low Power | 272 | Mass production |
| H9HKNNNBTUMUBR | 16Gb | x16 | 1.8V-1.1V-1.1V | L | Low Power | 366 | Mass production |
| H9HKNNNDGUMUAR | 24Gb | x16 | 1.8V-1.1V-1.1V | L | Low Power | 272 | Mass production |
| H9HKNNNDGUMUBR | 24Gb | x16 | 1.8V-1.1V-1.1V | L / M | Low Power | 366 | Mass production |
| H9HKNNNCTUMUAR | 32Gb | x16 | 1.8V-1.1V-1.1V | L | Low Power | 272 | Mass production |
| H9HKNNNCTUMUBR | 32Gb | x16 | 1.8V-1.1V-1.1V | L / M | Low Power | 366 | Mass production |
