XC3S400A-4FTG256C Spartan-3 FPGA Family : Complete Data Sheet list electronic items

XC3S400A-4FTG256C Spartan-3 FPGA Family : Complete Data Sheet list electronic items

Module 1: Introduction and Ordering Information

DS099-1 (v1.2) December 24, 2003 6 pages

• Introduction

• Features

• Architectural Overview

• Product Availability

• User I/O Chart

• Ordering Information

Module 2: Functional Description

DS099-2 (v1.2) July 11, 2003 40 pages

• IOBs - IOB Overview - SelectIO™ Signal Standards

• CLB Overview

• Block RAM

• Dedicated Multipliers

• Digital Clock Manager (DCM) - Clock Network

• Configuration

Introduction The Spartan™-3 family of Field-Programmable Gate Arrays is specifically designed to meet the needs of high volume, cost-sensitive consumer electronic applications. The eight-member family offers densities ranging from 50,000 to five million system gates, as shown in Table 1.

The Spartan-3 family builds on the success of the earlier Spartan-IIE family by increasing the amount of logic resources, the capacity of internal RAM, the total number of I/Os, and the overall level of performance as well as by improving clock management functions. Numerous enhancements derive from state-of-the-art Virtex™-II technology. These Spartan-3 enhancements, combined with advanced process technology, deliver more functionality and bandwidth per dollar than was previously possible, setting new standards in the programmable logic industry

Because of their exceptionally low cost, Spartan-3 FPGAs are ideally suited to a wide range of consumer electronics applications, including broadband access, home networking, display/projection and digital television equipment.

The Spartan-3 family is a superior alternative to mask programmed ASICs. FPGAs avoid the high initial cost, the lengthy development cycles, and the inherent inflexibility of conventional ASICs. Also, FPGA programmability permits design upgrades in the field with no hardware replacement necessary, an impossibility with ASICs.