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[China]
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Address: Room 405, Building A2, Niushang Zhigu, United Industrial Park, Fengtang Avenue, Shenzhen，Guangdong, China. Post code: 518100
Contact name:Amy
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AM3352BZCZD30 Microprocessor IC Sitara™ 1 Core, 32-Bit 300MHz
324-NFBGA (15x15)
Specifications of AM3352BZCZD30
| TYPE | DESCRIPTION |
| Category | Integrated Circuits (ICs) |
| Embedded | |
| Microprocessors | |
| Mfr | Texas Instruments |
| Series | Sitara™ |
| Package | Tray |
| Product Status | Active |
| Core Processor | ARM® Cortex®-A8 |
| Number of Cores/Bus Width | 1 Core, 32-Bit |
| Speed | 300MHz |
| Co-Processors/DSP | Multimedia; NEON™ SIMD |
| RAM Controllers | LPDDR, DDR2, DDR3, DDR3L |
| Graphics Acceleration | Yes |
| Display & Interface Controllers | LCD, Touchscreen |
| Ethernet | 10/100/1000Mbps (2) |
| SATA | - |
| USB | USB 2.0 + PHY (2) |
| Voltage - I/O | 1.8V, 3.3V |
| Operating Temperature | -40°C ~ 90°C (TJ) |
| Security Features | Cryptography, Random Number Generator |
| Mounting Type | Surface Mount |
| Package / Case | 324-LFBGA |
| Supplier Device Package | 324-NFBGA (15x15) |
| Additional Interfaces | CAN, I²C, McASP, McSPI, MMC/SD/SDIO, UART |
| Base Product Number | AM3352 |
Features of AM3352BZCZD30
• Up to 1-GHz Sitara™ ARM® Cortex®
-A8 32‑Bit RISC Processor
– NEON™ SIMD Coprocessor
– 32KB of L1 Instruction and 32KB of Data Cache With Single-Error
Detection (Parity)
– 256KB of L2 Cache With Error Correcting Code (ECC)
– 176KB of On-Chip Boot ROM
– 64KB of Dedicated RAM
– Emulation and Debug - JTAG
– Interrupt Controller (up to 128 Interrupt Requests)
• On-Chip Memory (Shared L3 RAM)
– 64KB of General-Purpose On-Chip Memory Controller (OCMC) RAM
– Accessible to All Masters
– Supports Retention for Fast Wakeup
• External Memory Interfaces (EMIF)
– mDDR(LPDDR), DDR2, DDR3, DDR3L Controller:
– mDDR: 200-MHz Clock (400-MHz Data Rate)
– DDR2: 266-MHz Clock (532-MHz Data Rate)
– DDR3: 400-MHz Clock (800-MHz Data Rate)
– DDR3L: 400-MHz Clock (800-MHz Data Rate)
– 16-Bit Data Bus
– 1GB of Total Addressable Space
– Supports One x16 or Two x8 Memory Device Configurations
– General-Purpose Memory Controller (GPMC)
– Flexible 8-Bit and 16-Bit Asynchronous Memory Interface With up
to Seven Chip Selects (NAND, NOR, Muxed-NOR, SRAM)
– Uses BCH Code to Support 4-, 8-, or 16-Bit ECC
– Uses Hamming Code to Support 1-Bit ECC
– Error Locator Module (ELM)
– Used in Conjunction With the GPMC to Locate Addresses of Data
Errors from Syndrome Polynomials Generated Using a BCH Algorithm
– Supports 4-, 8-, and 16-Bit per 512-Byte Block Error Location
Based on BCH Algorithms
Introduction of AM3352BZCZD30
• Gaming Peripherals
• Home and Industrial Automation
• Consumer Medical Appliances
• Printers
• Smart Toll Systems
• Connected Vending Machines
• Weighing Scales
• Educational Consoles
• Advanced Toys
