XC7Z010-1CLG400I Field Programmable Gate Array FPGA Chip SoC FPGA Core ARM Cortex A9

Zynq-7000 SoC

XC7Z010-1CLG400I FPGA Field Programmable Gate Array SoC FPGA Core ARM Cortex A9

Specifications

Description

The Zynq®-7000 family is based on the Xilinx SoC architecture. These products integrate a feature-rich dual-core

or single-core ARM® Cortex™-A9 based processing system (PS) and 28 nm Xilinx programmable logic (PL) in a

single device. The ARM Cortex-A9 CPUs are the heart of the PS and also include on-chip memory, external memory

interfaces, and a rich set of peripheral connectivity interfaces.

Features

ARM Cortex-A9 Based Application Processor Unit (APU)

• 2.5 DMIPS/MHz per CPU

• CPU frequency: Up to 1 GHz

• Coherent multiprocessor support

• ARMv7-A architecture

• TrustZone® security

• Thumb®-2 instruction set

• Jazelle® RCT execution Environment Architecture

• NEON™ media-processing engine

• Single and double precision Vector Floating Point Unit (VFPU)

• CoreSight™ and Program Trace Macrocell (PTM)

• Timer and Interrupts

• Three watchdog timers

• One global timer

• Two triple-timer counters Caches

• 32 KB Level 1 4-way set-associative instruction and data caches (independent for each CPU)

• 512 KB 8-way set-associative Level 2 cache (shared between the CPUs)

• Byte-parity support On-Chip Memory

• On-chip boot ROM

• 256 KB on-chip RAM (OCM)

• Byte-parity support External Memory Interfaces

• Multiprotocol dynamic memory controller

• 16-bit or 32-bit interfaces to DDR3, DDR3L, DDR2, or LPDDR2 memories

• ECC support in 16-bit mode

• 1GB of address space using single rank of 8-, 16-, or 32-bit-wide memories

• Static memory interfaces

• 8-bit SRAM data bus with up to 64 MB support

• Parallel NOR flash support

• ONFI1.0 NAND flash support (1-bit ECC)

• 1-bit SPI, 2-bit SPI, 4-bit SPI (quad-SPI), or two quad-SPI (8-bit) serial NOR flash 8-Channel DMA Controller

• Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and scatter-gather transaction support

Trading Guide