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MT48LC16M16A2P-6A IT G Dram Memory IC Chip 256Mbit 167MHz 135mA 7.5ns

Shenzhen Retechip Electronics Co., Ltd

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Contact name:Allen Wang

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MT48LC16M16A2P-6A IT G Dram Memory IC Chip 256Mbit 167MHz 135mA 7.5ns

Country/Region china
City & Province shenzhen guangdong
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Product Details

MT48LC16M16A2P-6A IT:G Dram memory chips 256 Mbit 167MHz 135mA 7.5ns TSOP-54

Specifications

Product AttributeAttribute Value
16 bit
16 M x 16
FBGA CodeD9NNF
167 MHz
7.5 ns
3.6 V
3 V
135 mA
- 40 C
+ 85 C

Description 

In general, 256Mb SDRAM devices (16 Meg x 4 x 4 banks, 8 Meg x 8 x 4 banks, and 4 Meg x 16 x 4 banks) are quad-bank DRAM that operate at 3.3V and include a synchronous interface. All signals are registered on the positive edge of the clock signal, CLK. Each of the x4’s 67,108,864-bit banks is organized as 8192 rows by 2048 columns by 4 bits. Each of the x8’s 67,108,864-bit banks is organized as 8192 rows by 1024 columns by 8 bits. Each of the x16’s 67,108,864-bit banks is organized as 8192 rows by 512 columns by 16 bits.

Read and write accesses to the SDRAM are burst-oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed se-quence. Accesses begin with the registration of an ACTIVE command, followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0 and BA1 select the bank, A[12:0] select the row). The address bits (x4: A[9:0], A11; x8: A[9:0]; x16: A[8:0]) reg-istered coincident with the READ or WRITE command are used to select the starting column location for the burst access.

Prior to normal operation, the SDRAM must be initialized. The following sections pro-vide detailed information covering device initialization, register definition, command descriptions, and device operation.

Address Table

Features

• PC100- and PC133-compliant

• Fully synchronous; all signals registered on positive edge of system clock

• Internal, pipelined operation; column address can be changed every clock cycle

• Internal banks for hiding row access/precharge

• Programmable burst lengths: 1, 2, 4, 8, or full page

• Auto precharge, includes concurrent auto precharge and auto refresh modes

• Self refresh mode (not available on AT devices)

• Auto refresh

  – 64ms, 8192-cycle refresh (commercial and industrial)

  – 16ms, 8192-cycle refresh (automotive)

• LVTTL-compatible inputs and outputs

• Single 3.3V ±0.3V power supply

Trading Guides                                                               

ShippingDelivery period

 For in-stock parts, orders are estimated to ship out in 3 days.
 Once shipped, estimated delivery time depends on the below   carriers you chose:
 DHL Express, 3-7 business days.
 DHL eCommerce,12-22 business days.
 FedEx International Priority, 3-7 business days
 EMS, 10-15 business days.
 Registered Air Mail, 15-30 business days.

Shipping rates

 After confirming the order, we will evaluate the shipping cost   based on the weight of the goods

Shipping option

 We provide DHL, FedEx, EMS, SF Express, and Registered     Air Mail international shipping.

Shipping tracking

  We will notify you by email with tracking number once order   is shipped.

Returning

warranty

Returning

  Returns are normally accepted when completed within 30   days from date of shipment.Parts should be unused and in   original packaging.Customer has to take charge for the   shipping.

Warranty

 All Retechip purchases come with a 30-day money-back   return policy, This warranty shall not apply to any item where   defects have been caused by improper customer assembly,   failure by customer to follow instructions, product   modification, negligent or improper operation

Ordering

 

Payment

 

 T/T,PayPal, Credit Card includes Visa, Master, American   Express.

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