SAB80C166-M # 16-Bit CMOS Single - Chip Microcontroller Infineon brand
Technologies AG High Performance
Parameters Introduce :
● High Performance 16-bit CPU with 4-Stage Pipeline
● 100 ns Instruction Cycle Time at 20 MHz CPU Clock
● 500 ns Multiplication (16 × 16 bit), 1 µs Division (32 / 16 bit)
● Enhanced Boolean Bit Manipulation Facilities
● Register-Based Design with Multiple Variable Register Banks
● Single-Cycle Context Switching Support
● Up to 256 KBytes Linear Address Space for Code and Data
● 1 KByte On-Chip RAM
● 32 KBytes On-Chip ROM (SAB 83C166 only)
● Programmable External Bus Characteristics for Different Address
Ranges
● 8-Bit or 16-Bit External Data Bus
● Multiplexed or Demultiplexed External Address/Data Buses
● Hold and Hold-Acknowledge Bus Arbitration Support
● 512 Bytes On-Chip Special Function Register Area
● Idle and Power Down Modes
● 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities
via Peripheral Event
Controller (PEC)
● 16-Priority-Level Interrupt System
● 10-Channel 10-bit A/D Converter with 9.7 µs Conversion Time
● 16-Channel Capture/Compare Unit
● Two Multi-Functional General Purpose Timer Units with 5 Timers
● Two Serial Channels (USARTs)
● Programmable Watchdog Timer
● Up to 76 General Purpose I/O Lines
● Supported by a Wealth of Development Tools like C-Compilers,
Macro-Assembler Packages,
Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic
Analyzer Disassemblers,
Programming Boards
● On-Chip Bootstrap Loader
● 100-Pin Plastic MQFP Package (EIAJ)
Functional Description
The architecture of the SAB 80C166 combines advantages of both RISC
and CISC processors and
of advanced peripheral subsystems in a very well-balanced way. The
following block diagram gives
an overview of the different on-chip components and of the
advanced, high bandwidth internal bus
structure of the SAB 80C166.
Note: All time specifications refer to a CPU clock of 20 MHz (see
definition in the AC Characteristics section)
Memory Organization
The memory space of the SAB 80C166 is configured in a Von Neumann
architecture which means
that code memory, data memory, registers and I/O ports are
organized within the same linear
address space which includes 256 KBytes. Address space expansion to
16 MBytes is provided for
future versions. The entire memory space can be accessed bytewise
or wordwise. Particular
portions of the on-chip memory have additionally been made directly
bit addressable.
The SAB 83C166 contains 32 KBytes of on-chip mask-programmable ROM
for code or constant
data. The ROM can be mapped to either segment 0 or segment 1.
1 KByte of on-chip RAM is provided as a storage for user defined
variables, for the system stack,
general purpose register banks and even for code. A register bank
can consist of up to 16 wordwide
(R0 to R15) and/or bytewide (RL0, RH0, …, RL7, RH7) so-called
General Purpose Registers (GPRs).
512 bytes of the address space are reserved for the Special
Function Register area. SFRs are
wordwide registers which are used for controlling and monitoring
functions of the different on-chip
units. 98 SFRs are currently implemented. Unused SFR addresses are
reserved for future
members of the SAB 80C166 family.
In order to meet the needs of designs where more memory is required
than is provided on chip, up
to 256 KBytes of external RAM and/or ROM can be connected to the
microcontroller.
Deli electronics tehcnology Co.,Ltd.
www.icmemorychip.com
www.deli-ic.com
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