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Iso / Dis 19675 Paut Ultrasonic Calibration Block Carbon Steel 1018

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Iso / Dis 19675 Paut Ultrasonic Calibration Block Carbon Steel 1018

City & Province	beijing beijing
Categories	Other Metals & Metal Products

Product Details

Carbon Steel 1018 ISO/DIS 19675 PAUT Calibration Block Ultrasonic Calibration Block

Standard ISO/DIS 19675:2017 specifies the requirements for the dimensions, material and manufactures of a steel block for calibrating ultrasonic test equipment used in ultrasonic testing with phased array technology.

HUATEC brand ISO/DIS 19765 block material: carbon steel 1018, stainless steel 304/316, duplex stainless steel 2205,aluminum 6063/7075,nodular cast iron and other materials.

Mark: HUATEC and OEM can be done

The basic verification of PAUT ultrasonic calibration block: material velocity verification, wedge delay verification and Angle correction gain verification

Further requirements of the PAUT ultrasonic calibration block:

It needs to be lightweight, cost-effective and meet the requirements of international regulations;

Can check the phased array probe according to other ISO standards;

Customer can quickly and simply check and confirm that the ultrasonic characteristics of test blocks meet the requirements.

Two appendices were included in ISO 19675 to enable operators to quickly understand the appropriate use of the new PAUT test block.

Appendix A is A normative appendix that describes the measurement method of material anisotropy and instructs the test block maker how to determine the speed of sound (these values are required to be included in the technical documentation provided with the test block to the user for verification and acceptance by the operator).

Appendix B is a reference appendix. The purpose is to compare PAUT test blocks with ISO2400 test blocks (i.e., to compare old and new IIW test blocks), and to briefly explain some other possible uses, such as PA probe wedge delay assessment, petal assessment, active array element assessment, sensitivity equalization, data mapping verification, phased array element configuration, etc.