TMS320C6678CYP Electronic IC Chips Multicore Fixed and Floating-Point Digital Signal Processor

TMS320C6678

Multicore Fixed and Floating-Point Digital Signal Processor

Features

• Eight TMS320C66x™ DSP Core Subsystems (C66x CorePacs), Each with

  – 1.0 GHz or 1.25 GHz C66x Fixed/Floating-Point CPU Core

    › 40 GMAC/Core for Fixed Point @ 1.25 GHz

    › 20 GFLOP/Core for Floating Point @ 1.25 GHz

  – Memory

    › 32K Byte L1P Per Core

    › 32K Byte L1D Per Core

    › 512K Byte Local L2 Per Core

• Multicore Shared Memory Controller (MSMC)

  – 4096KB MSM SRAM Memory Shared by Eight DSP C66x CorePacs

  – Memory Protection Unit for Both MSM SRAM and DDR3_EMIF

• Multicore Navigator

  – 8192 Multipurpose Hardware Queues with Queue Manager

  – Packet-Based DMA for Zero-Overhead Transfers

• Network Coprocessor

  – Packet Accelerator Enables Support for

    › Transport Plane IPsec, GTP-U, SCTP, PDCP

    › L2 User Plane PDCP (RoHC, Air Ciphering)

    › 1-Gbps Wire-Speed Throughput at 1.5 MPackets Per Second

  – Security Accelerator Engine Enables Support for

    › IPSec, SRTP, 3GPP, WiMAX Air Interface, and SSL/TLS Security

    › ECB, CBC, CTR, F8, A5/3, CCM, GCM, HMAC, CMAC, GMAC, AES, DES, 3DES,

      Kasumi, SNOW 3G, SHA-1, SHA-2 (256-bit Hash), MD5

    › Up to 2.8 Gbps Encryption Speed

• Peripherals

  – Four Lanes of SRIO 2.1

    › 1.24/2.5/3.125/5 GBaud Operation Supported Per Lane

    › Supports Direct I/O, Message Passing

    › Supports Four 1×, Two 2×, One 4×, and Two 1× + One 2× Link Configurations

  – PCIe Gen2

    › Single Port Supporting 1 or 2 Lanes

    › Supports Up To 5 GBaud Per Lane

  – HyperLink

    › Supports Connections to Other KeyStone Architecture Devices Providing Resource Scalability

    › Supports up to 50 Gbaud

  – Gigabit Ethernet (GbE) Switch Subsystem

    › Two SGMII Ports

    › Supports 10/100/1000 Mbps Operation

  – 64-Bit DDR3 Interface (DDR3-1600)

    › 8G Byte Addressable Memory Space

  – 16-Bit EMIF

  – Two Telecom Serial Ports (TSIP)

    › Supports 1024 DS0s Per TSIP

    › Supports 2/4/8 Lanes at 32.768/16.384/8.192 Mbps Per Lane

  – UART Interface

  – I2 C Interface

  – 16 GPIO Pins

  – SPI Interface

  – Semaphore Module

  – Sixteen 64-Bit Timers

  – Three On-Chip PLLs

• Commercial Temperature:

  – 0°C to 85°C

• Extended Temperature:

  – - 40°C to 100°C

1.1 KeyStone Architecture

TI’s KeyStone Multicore Architecture provides a high performance structure for integrating RISC and DSP cores with application specific coprocessors and I/O. KeyStone is the first of its kind that provides adequate internal bandwidth for nonblocking access to all processing cores, peripherals, coprocessors, and I/O. This is achieved with four main hardware elements: Multicore Navigator, TeraNet, Multicore Shared Memory Controller, and HyperLink.

Multicore Navigator is an innovative packet-based manager that controls 8192 queues. When tasks are allocated to the queues, Multicore Navigator provides hardware-accelerated dispatch that directs tasks to the appropriate available hardware. The packet-based system on a chip (SoC) uses the two Tbps capacity of the TeraNet switched central resource to move packets. The Multicore Shared Memory Controller enables processing cores to access shared memory directly without drawing from TeraNet’s capacity, so packet movement cannot be blocked by memory access.

HyperLink provides a 50-Gbaud chip-level interconnect that allows SoCs to work in tandem. Its low-protocol overhead and high throughput make HyperLink an ideal interface for chip-to-chip interconnections. Working with Multicore Navigator, HyperLink dispatches tasks to tandem devices transparently and executes tasks as if they are running on local resources.

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