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MCIMX537CVV8C Transistor Ic Chip Ic Mpu I.Mx53 800mhz 529fbga

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MCIMX537CVV8C Transistor Ic Chip Ic Mpu I.Mx53 800mhz 529fbga

Country/Region	china
City & Province	shenzhen guangdong
Categories	Voltage Regulators/Stabilizers

Product Details

MCIMX537CVV8C Transistor Ic Chip Ic Mpu I.Mx53 800mhz 529fbga

ARM® Cortex®-A8 Microprocessor IC i.MX53 1 Core, 32-Bit 800MHz 529-FBGA (19x19)

Specifications of MCIMX537CVV8C

TYPE	DESCRIPTION
Category	Integrated Circuits (ICs)
	Embedded
	Microprocessors
Mfr	NXP USA Inc.
Series	i.MX53
Package	Tray
Product Status	Obsolete
Core Processor	ARM® Cortex®-A8
Number of Cores/Bus Width	1 Core, 32-Bit
Speed	800MHz
Co-Processors/DSP	Multimedia; NEON™ SIMD
RAM Controllers	LPDDR2, DDR2, DDR3
Graphics Acceleration	Yes
Display & Interface Controllers	Keypad, LCD
Ethernet	10/100Mbps (1)
SATA	SATA 1.5Gbps (1)
USB	USB 2.0 (2), USB 2.0 + PHY (2)
Voltage - I/O	1.3V, 1.8V, 2.775V, 3.3V
Operating Temperature	-40°C ~ 85°C (TA)
Security Features	ARM TZ, Boot Security, Cryptography, RTIC, Secure Fusebox, Secure JTAG, Secure Memory, Secure RTC, Tamper Detection
Mounting Type	Surface Mount
Package / Case	529-FBGA
Supplier Device Package	529-FBGA (19x19)
Additional Interfaces	1-Wire, AC'97, CAN, I²C, I²S, MMC/SD, SAI, SPI, SSI, UART
Base Product Number	MCIMX537

Features of MCIMX537CVV8C

The i.MX53 multimedia applications processor (AP) is based on the ARM Platform,which has thefollowing features:

• MMU, L1 instruction and L1 data cache

• Unified L2 cache

• Maximum frequency of the core (including Neon, VFPv3 and L1 cache): 800 MHz

• Neon coprocessor (SIMD media processing architecture) and vector floating point(VFP-Lite) coprocessor supporting VFPv3

• TrustZone The memory system consists of the following components:

• Level 1 cache:

— Instruction (32 Kbyte)

— Data (32 Kbyte)

• Level 2 cache:

— Unified instruction and data (256 Kbyte)

• Level 2 (internal) memory:

— Boot ROM, including HAB (64 Kbyte)

— Internal multimedia/shared, fast access RAM (128 Kbyte)

— Secure/non-secure RAM (16 Kbyte)

• External memory interfaces:

— 16/32-bit DDR2-800, LV-DDR2-800 or DDR3-800 up to 2 Gbyte

— 32-bit LPDDR2

— 8/16-bit NAND SLC/MLC Flash, up to 66 MHz, 4/8/14/16-bit ECC

— 8/16-bit NOR Flash, PSRAM, and cellular RAM.

— 32-bit multiplexed mode NOR Flash, PSRAM & cellular RAM.

— 8-bit Asynchronous (DTACK mode) EIM interface.

— All EIM pins are muxed on other interfaces (data with NFC pins). I/O muxing logic selects EIM port, as primary muxing at system boot.

— Samsung OneNAND™ and managed NAND including eMMC up to rev 4.4 (in muxed I/Omode)

The i.MX53 system is built around the following system on chip interfaces:

• 64-bit AMBA AXI v1.0 bus—used by ARM platform, multimedia accelerators (such as VPU, IPU,GPU3D, GPU2D) and the external memory controller (EXTMC) operating at 200 MHz.

• 32-bit AMBA AHB 2.0 bus—used by the rest of the bus master peripherals operating at 133 MHz.

• 32-bit IP bus—peripheral bus used for control (and slow data traffic) of the most system peripheral devices operating at 66 MHz.

Applications of MCIMX537CVV8C

— Three I2S/SSI/AC97 ports, supporting up to 1.4 Mbps, each connected to audio

multiplexer

(AUDMUX) providing four external ports.

— Five UART RS232 ports, up to 4.0 Mbps each. One supports 8-wire, the other four

support

4-wire.

— Two high speed enhanced CSPI (ECSPI) ports plus one CSPI port

— Three I2

C ports, supporting 400 kbps