LATTICE 1048 Device Embedded CPLDs Complex Programmable Logic Devices Chip ISPLSI1048C-50LG/883

1048 device embedded-CPLDs complex programmable logic devices chip from LATTICE ISPLSI1048C-50LG/883

Features

• HIGH-DENSITY PROGRAMMABLE LOGIC

— 8000 PLD Gates

— 96 I/O Pins, 12 Dedicated Inputs, 2 Global Output

Enables

— 288 Registers

— High-Speed Global Interconnect

— Wide Input Gating for Fast Counters, State

Machines, Address Decoders, etc.

— Small Logic Block Size for Random Logic

— Security Cell Prevents Unauthorized Copying

• HIGH PERFORMANCE E2CMOS® TECHNOLOGY

— fmax = 50 MHz Maximum Operating Frequency

— tpd = 22 ns Propagation Delay

— TTL Compatible Inputs and Outputs

— Electrically Erasable and Reprogrammable

— Non-Volatile E2CMOSTechnology

— 100% Tested at Time of Manufacture

• IN-SYSTEM PROGRAMMABLE

— In-System Programmable™ (ISP™) 5-Volt Only

— Increased Manufacturing Yields, Reduced Time-to-

Market, and Improved Product Quality

— Reprogram Soldered Devices for Faster Debugging

• COMBINES EASE OF USE AND THE FAST SYSTEM

SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY

OF FIELD PROGRAMMABLE GATE ARRAYS

— Complete Programmable Device Can Combine Glue

Logic and Structured Designs

— Four Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

Interconnectivity

• ispDesignEXPERT™ – LOGIC COMPILER AND COMPLETE

ISP DEVICE DESIGN SYSTEMS FROM HDL

SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING

— Superior Quality of Results

— Tightly Integrated with Leading CAE Vendor Tools

— Productivity Enhancing Timing Analyzer, Explore

Tools, Timing Simulator and isp ANALYZER™

— PC and UNIX Platforms

Description

The ispLSI 1048C/883 is a High-Density Programmable

Logic Device processed in full compliance to MIL-STD-

883. This military grade device contains 288 Registers,

96 Universal I/O pins, 12 Dedicated Input pins, two

Global Output Enables (GOE), four Dedicated Clock

Input pins and a Global Routing Pool (GRP). The GRP

provides complete interconnectivity between all of these

elements. The isp LSI 1048C/883 features 5-Volt in system

programming and in-system diagnostic

capabilities.

Information :

It is the first device which offers non-volatile

reprogrammability of the logic, and the interconnect to

provide truly reconfigurable systems. Compared to the

ispLSI 1048, the ispLSI 1048C/883 offers two additional

dedicated inputs and two new Global Output Enable pins.

The basic unit of logic on the ispLSI 1048C/883 device is

the Generic Logic Block (GLB). The GLBs are labeled A0,

A1 .. F7 in figure 1. There are a total of 48 GLBs in the

ispLSI 1048C/883 devices. Each GLB has 18 inputs, a

programmable AND/OR/XOR array, and four outputs

which can be configured to be either combinatorial or

registered. Inputs to the GLB come from the GRP and

dedicated inputs. All of the GLB outputs are brought back

into the GRP so that they can be connected to the inputs

of any other GLB on the device.

Absolute Maximum Ratings 1

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