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SMD0805 Chip Varistor SV0805N9R0G0A Typically Applied Protect
Integrated Circuits
Chip Varistor DATASHEET: SV0805N9R0G0A_v2201.1.pdf
Description:
The Chip Varistor SV0805N9R0G0A is based on Multilayer fabrication
technology. These components are designed to suppress a variety of
transient events, including those specified in IEC 61000-4-2 or
other standards used for Electromagnetic Compliance (EMC). The
SV0805N9R0G0A is typically applied to protect integrated circuits
and other components at the circuit board level. It can operate
over a wider temperature range than zener diodes.
Chip Varistor Electrical Characteristics (25±5℃):
| Symbol | Minimum | Typical | Maximum | Units |
| VRMS | — | — | 6 | V |
| VDC | — | — | 9 | V |
| VV | 10.8 | — | 16.2 | V |
| VC | — | — | 35.6 | V |
| Imax | — | — | 50 | A |
| Wmax | — | — | 0.2 | J |
VRMS - Maximum AC operating voltage the varistor can maintain and
not exceed 10μA leakage current.
VDC - Maximum DC operating voltage the varistor can maintain and
not exceed 10μA leakage current.
VV - Voltage across the device measure at 1mA DC current.
Equivalent to VB “breakdown voltage”.
VC - Maximum peak current across the varistor with 8/20μs waveform
and 2A pulse current.
Imax - Maximum peak current which may be applied with 8/20μs
waveform without device failure.
Wmax - Maximum energy which may be dissipated with the 10/1000μs
waveform without device failure.
Chip Varistor Features:
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Chip Varistor Applications:
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Chip Varistor Construction & Dimensions:
| Size EIA (EIAJ) | Length (L) | Width (W) | Thickness (T) | |||
| Inches | Millimeters | Inches | Millimeters | Inches | Millimeters | |
| 0805 (2012) | 0.079±0.008 | 2.00±0.20 | 0.049±0.008 | 1.25±0.20 | 0.055 Max | 1.40 Max |
Chip Varistor IR Soldering:
| Rapid heating, partial heating or rapid cooling will easily cause defect of the component. So preheating and gradual cooling process is suggested. IR soldering has the highest yields due to controlled heating rates and solder liquidus times. Make sure that the element is not subjected to a thermal gradient steeper than 4 degrees per second. 2 degrees per second is the ideal gradient. During the soldering process, pre-heating to within 100 degrees of the solder peak temperature is essential to minimize thermal shock. |
Chip Varistor Environmental & Reliability Testing:
| Characteristic | Test method and description | |||
| High Temperature Storage | The specimen shall be subjected to125±2℃ for 1000±2 hours in a thermostatic bath without load and then stored at room temperature and humidity for 1 to 2 hours. The change of varistor voltage shall be within 10%. | |||
| Temperature Cycle | The temperature cycle of specified temperature shall be repeated five times and then stored at room temperature and humidity for one two hours. The change of varistor voltage shall be within 10% and mechanical damage shall be examined. | Step | Temperture | Period |
| 1 | -40±3℃ | 30min±3 | ||
| 2 | Room Temperature | 1~2hours | ||
| 3 | 125±2℃ | 30min±3 | ||
| 4 | Room Temperature | 1~2hours | ||
| High Temperature Load | After being continuously applied the maximum allowable voltage at 85℃ for 1000hours, the specimen shall be stored at room temperature and humidity for one or hours, the change of varistor voltage shall be within 10%. | |||
Damp Heat Load/ Humidity Load | The specimen should be subjected to 40℃,90 to 95%RH environment, and the maximum allowable voltage applied for 1000 hours, then stored at room temperature and humidity for one or two hours. The change of varistor voltage shall be within 10%. | |||
| Low Temperature Storage | The specimen should be subjected to -40℃, without load for 1000 hours and then stored at room temperature for one two hours. The change of varistor voltage shall be within 10%. | |||
Quantity of Products in The Taping Package:
| SIZE EIA (EIAJ) | 0805 (2012) |
| Standard Packing Quantity (PCS / reel) | 4,000 |
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