Integrated Circuits EP1S10F780I6N IC FPGA 426 I/O 780FBGA Field
Programmable Gate Arrays Electronic Components
Functional Description :
Stratix® devices contain a two-dimensional row- and column-based architecture to implement custom logic. A series of column and row
interconnects of varying length and speed provide signal interconnects between logic array blocks (LABs), memory block structures, and DSP
blocks.
The logic array consists of LABs, with 10 logic elements (LEs) in each LAB. An LE is a small unit of logic providing efficient
implementation of
user logic functions. LABs are grouped into rows and columns across
the device.
M512 RAM blocks are simple dual-port memory blocks with 512 bits plus parity (576 bits). These blocks provide dedicated simple dual-port or
single-port memory up to 18-bits wide at up to 318 MHz. M512 blocks are grouped into columns across the device in between certain LABs.
M4K RAM blocks are true dual-port memory blocks with 4K bits plus parity (4,608 bits). These blocks provide dedicated true dual-port, simple
dual-port, or single-port memory up to 36-bits wide at up to 291 MHz. These blocks are grouped into columns across the device in between
certain LABs.
M-RAM blocks are true dual-port memory blocks with 512K bits plus parity (589,824 bits). These blocks provide dedicated true dual-port,
simple dual-port, or single-port memory up to 144-bits wide at up to 269 MHz. Several M-RAM blocks are located individually or in pairs
within the device’s logic array.
Digital signal processing (DSP) blocks can implement up to either eight full-precision 9 × 9-bit multipliers, four full-precision 18 × 18-bit
multipliers, or one full-precision 36 × 36-bit multiplier with add or subtract features. These blocks also contain 18-bit input shift registers for
digital signal processing applications, including FIR and infinite
impulse response (IIR) filters. DSP blocks are grouped into two
columns in each
device.
Each Stratix device I/O pin is fed by an I/O element (IOE) located at the end of LAB rows and columns around the periphery of the device. I/O
pins support numerous single-ended and differential I/O standards. Each IOE contains a bidirectional I/O buffer and six registers for
registering input, output, and output-enable signals. When used with dedicated clocks, these registers provide exceptional performance
and interface support with external memory devices such as DDR SDRAM, FCRAM, ZBT, and QDR SRAM devices.
High-speed serial interface channels support transfers at up to 840 Mbps using LVDS, LVPECL, 3.3-V PCML, or HyperTransport technology I/O
standards.
Stratix Device Features :
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