SAK-TC277TP-64F200N Dc AURIX Microcontroller Chip Ic 32-Bit Tri-Core 200MHz 4MB 4M X 8 FLASH PG-LFBGA-292-6

SAK-TC277TP-64F200N TriCore™ AURIX™ Microcontroller IC 32-Bit Tri-Core 200MHz 4MB (4M x 8) FLASH PG-LFBGA-292-6

Datasheet:SAK-TC277TP-64F200N

Summary of Features

The TC27x product family has the following features:

• High Performance Microcontroller with three CPU cores

• Two 32-bit super-scalar TriCore CPUs (TC1.6P), each having the following features:

– Superior real-time performance

– Strong bit handling

– Fully integrated DSP capabilities

– Multiply-accumulate unit able to sustain 2 MAC operations per cycle

– Fully pipelined Floating point unit (FPU)

– up to 200 MHz operation at full temperature range

– up to 120 Kbyte Data Scratch-Pad RAM (DSPR)

– up to 32 Kbyte Instruction Scratch-Pad RAM (PSPR)

– 16 Kbyte Instruction Cache (ICACHE)

– 8 Kbyte Data Cache (DCACHE)

• Power Efficient scalar TriCore CPU (TC1.6E), having the following features:

– Binary code compatibility with TC1.6P

– up to 200 MHz operation at full temperature range

– up to 112 Kbyte Data Scratch-Pad RAM (DSPR)

– up to 24 Kbyte Instruction Scratch-Pad RAM (PSPR)

– 8 Kbyte Instruction Cache (ICACHE)

– 0.125Kbyte Data Read Buffer (DRB)

• Lockstepped shadow cores for one TC1.6P and for TC1.6E

• Multiple on-chip memories

– All embedded NVM and SRAM are ECC protected

– up to 4 Mbyte Program Flash Memory (PFLASH)

– up to 384 Kbyte Data Flash Memory (DFLASH) usable for EEPROM emulation

– 32 Kbyte Memory (LMU)

– BootROM (BROM)

• 64-Channel DMA Controller with safe data transfer

• Sophisticated interrupt system (ECC protected)

• High performance on-chip bus structure

– 64-bit Cross Bar Interconnect (SRI) giving fast parallel access between bus masters, CPUs and memories

– 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units

– One bus bridge (SFI Bridge)

• Optional Hardware Security Module (HSM) on some variants

• Safety Management Unit (SMU) handling safety monitor alarms

• Memory Test Unit with ECC, Memory Initialization and MBIST functions (MTU)

• Hardware I/O Monitor (IOM) for checking of digital I/O

• Versatile On-chip Peripheral Units

– Four Asynchronous/Synchronous Serial Channels (ASCLIN) with hardware LIN support (V1.3, V2.0, V2.1 and J2602) up to 50 MBaud

– Four Queued SPI Interface Channels (QSPI) with master and slave capability up to 50 Mbit/s

– High Speed Serial Link (HSSL) for serial inter-processor communication up to 320 Mbit/s

– Two serial Micro Second Bus interfaces (MSC) for serial port expansion to external power devices

– One MultiCAN+ Module with 4 CAN nodes and 256 free assignable message objects for high efficiency data handling via FIFO buffering and gateway data transfer

– 10 Single Edge Nibble Transmission (SENT) channels for connection to sensors

– One FlexRayTM module with 2 channels (E-Ray) supporting V2.1

– One Generic Timer Module (GTM) providing a powerful set of digital signal filtering and timer functionality to realize autonomous and complex Input/Output management

– One Capture / Compare 6 module (Two kernels CCU60 and CCU61)

– One General Purpose 12 Timer Unit (GPT120)

– Three channel Peripheral Sensor Interface conforming to V1.3 (PSI5)

– Peripheral Sensor Interface with Serial PHY (PSI5-S)

– Optional Inter-Integrated Circuit Bus Interface (I2C) conforming to V2.1

– Optional IEEE802.3 Ethernet MAC with RMII and MII interfaces (ETH)

• Versatile Successive Approximation ADC (VADC)

– Cluster of 8 independent ADC kernels

– Input voltage range from 0 V to 5.5V (ADC supply)

• Delta-Sigma ADC (DSADC) – Six channels

• Digital programmable I/O ports

• On-chip debug support for OCDS Level 1 (CPUs, DMA, On Chip Buses)

• multi-core debugging, real time tracing, and calibration

• four/five wire JTAG (IEEE 1149.1) or DAP (Device Access Port) interface

• Power Management System and on-chip regulators

• Clock Generation Unit with System PLL and Flexray PLL

• Embedded Voltage Regulator

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