Gate Array Electronic Integrated Circuits Field Programmable ECP3 Lattice

LFE3-17EA-6FTN256I Field Programmable Gate Array ECP3 Lattice

Features
 Higher Logic Density for Increased System
Integration
• 17K to 149K LUTs
• 116 to 586 I/Os
 Embedded SERDES
• 150 Mbps to 3.2 Gbps for Generic 8b10b, 10-bit
SERDES, and 8-bit SERDES modes
• Data Rates 230 Mbps to 3.2 Gbps per channel
for all other protocols
• Up to 16 channels per device: PCI Express,
SONET/SDH, Ethernet (1GbE, SGMII, XAUI),
CPRI, SMPTE 3G and Serial RapidIO
 sysDSP™
• Fully cascadable slice architecture
• 12 to 160 slices for high performance multiply
and accumulate
• Powerful 54-bit ALU operations
• Time Division Multiplexing MAC Sharing
• Rounding and truncation
• Each slice supports
—Half 36x36, two 18x18 or four 9x9 multipliers
—Advanced 18x36 MAC and 18x18 Multiply-
Multiply-Accumulate (MMAC) operations
 Flexible Memory Resources
• Up to 6.85Mbits sysMEM™ Embedded Block
RAM (EBR)
• 36K to 303K bits distributed RAM
 sysCLOCK Analog PLLs and DLLs
• Two DLLs and up to ten PLLs per device
 Pre-Engineered Source Synchronous I/O
• DDR registers in I/O cells
• Dedicated read/write levelling functionality
• Dedicated gearing logic
• Source synchronous standards support
—ADC/DAC, 7:1 LVDS, XGMII
—High Speed ADC/DAC devices
• Dedicated DDR/DDR2/DDR3 memory with DQS
support
• Optional Inter-Symbol Interference (ISI) 
correction on outputs
 Programmable sysI/O™ Buffer Supports
Wide Range of Interfaces
• On-chip termination
• Optional equalization filter on inputs
• LVTTL and LVCMOS 33/25/18/15/12
• SSTL 33/25/18/15 I, II
• HSTL15 I and HSTL18 I, II
• PCI and Differential HSTL, SSTL
• LVDS, Bus-LVDS, LVPECL, RSDS, MLVDS
 Flexible Device Configuration
• Dedicated bank for configuration I/Os
• SPI boot flash interface
• Dual-boot images supported
• Slave SPI
• TransFR™ I/O for simple field updates
• Soft Error Detect embedded macro
 System Level Support
• IEEE 1149.1 and IEEE 1532 compliant
• Reveal Logic Analyzer
• ORCAstra FPGA configuration utility
• On-chip oscillator for initialization & general use
• 1.2 V core power supply
Table 1-1. LatticeECP3™ Family Selection Guide
Device ECP3-17 ECP3-35 ECP3-70 ECP3-95 ECP3-150
LUTs (K) 17 33 67 92 149
sysMEM Blocks (18 Kbits) 38 72 240 240 372
Embedded Memory (Kbits) 700 1327 4420 4420 6850
Distributed RAM Bits (Kbits) 36 68 145 188 303
18 x 18 Multipliers 24 64 128 128 320
SERDES (Quad) 1 1 3 3 4
PLLs/DLLs 2 / 2 4 / 2 10 / 2 10 / 2 10 / 2
Packages and SERDES Channels/ I/O Combinations
328 csBGA (10 x 10 mm) 2 / 116
256 ftBGA (17 x 17 mm) 4 / 133 4 / 133
484 fpBGA (23 x 23 mm) 4 / 222 4 / 295 4 / 295 4 / 295
672 fpBGA (27 x 27 mm) 4 / 310 8 / 380 8 / 380 8 / 380
1156 fpBGA (35 x 35 mm) 12 / 490 12 / 490 16 / 586

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