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8 Inch Silicon Wafer FZ N Type Phosphorus Doped Orientation 100 Prime Grade 8"

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XIAMEN POWERWAY ADVANCED MATERIAL CO., LTD.

8 Inch Silicon Wafer FZ N Type Phosphorus Doped Orientation 100 Prime Grade 8"

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8 Inch Silicon Wafer FZ N Type Phosphorus Doped Orientation 100 Prime Grade 8"

 

PAM-XIAMEN is a manufacturer of CZ and FZ silicon wafer, we now become the worldwide source for high pure silicon wafers,thermal oxide silicon and epi wafers. Silicon wafer is used for integrated circuits , detector / sensor device , MEMS fabrication, opto-electronic components, and solar cells and finally apply to computer, mobile, sensor and other electronics. With rich experiences , PAM-XIAMEN understand your requirements and can provide exactly the silicon products you need with the suitable quality and lowest possible price . PAM-XIAMEN can provide both standard and customized silicon wafers to meet your demands.PAM-XIAMEN offer semiconductor silicon wafer with diameters from 1’’ (25.4 mm) to 12’’ (300 mm). We work either Cz (Czochralski) or FZ (Float Zone) silicon wafers. The polishing process is also made according to SEMI standard( the Semiconductor Equipment and Materials International standards). We also work ultra thin wafer, silicon oxide wafer SiO2 thin film, silicon nitride wafer Si3N4 thin film, thin film deposition and metallization on silicon wafers.

 

8inch Silicon Wafer FZ N Type Phosphorus Doped Orientation 100 Prime Grade 8"

TypeConduction TypeOrientationDiameter(mm)Resistivity(Ω•cm)
High resistanceN&P<100>&<111>50 - 300>1000
NTDN<100>&<111>50 - 30030-800
CFZN&P<100>&<111>50 - 3001-50
GDN&P<100>&<111>50 - 3000.001-300

 

ParameterUnitValue
Crystalline structure-Monocrystalline
Growth technique-FZ
Crystal Orientation-100±0.5°
Conductance type-N
Dopant-Phosphorus
Diametermm200±0.2 mm
ResistivityΩ/cm28000-14000Ωcm
Thicknessum625±5µm
TTVum≤6 um
BOWum≤35 um
Warpum≤35 um
Site Flatness SFQDum20X20mm: 0.40um
Surface Metals (Al,Ca,Cu,Fe,Ni,Zn,Cr,Na)Atoms/cm2Max 5E10/cm2
(G)STIRumCustomer standard
Site Flatness-STIRumCustomer standard
Metrology edge exclusion
(lpd’s, mechanical parameters)
mm3
LPD's-LPDs >= 0,30 µm (including COP’s) <=25
LPDs >= 0,20 µm (including COP’s) <=30
LPDs >= 0,16 µm (including COP’s) <=60
Oxygen Concentrationppma11-15 PPMA
Carbon Concentrationppma<1E16/cc
RRG-≤15%
Front Surface-Polished
Back Surface-Polished
Edge Surface Condition SEMI STD or Customer Request
Notch-SEMI STD
Laser mark-SEMI STD or Customer Request
Packaging Packaged in a class 100 clean room environment,
Heat-sealed plastic inner/aluminium foil outer bags,
Vacuum Packing
If specific requirement by customer, will adjust accordingly
ParameterUnitValue

 

How is Silicon Wafer Made?

Growth of Silicon Ingot: single crystal silicon wafers grow via the Czochralski (CZ) and FZ method,CZ ingot growth requires chunks of virgin polycrystalline silicon, depending on the dopant, the ingot becomes a P or N type ingot (boron: P type; Phosphorus, antimony, arsenic: N type).

 

Slicing:Once the ingot is fully-grown, it is ground to a rough size diameter that is slightly larger than the target diameter of the final silicon wafer. The ingot has a notch or flat cut into it, the ingot proceeds to slicing. The diamond edge saw helps to minimize damage to the wafers, thickness variation, and bow and warp defects.

After the wafers have been sliced, the lapping process begins.

Cleaning:The final and most crucial step in the manufacturing process is polishing the wafer. This process takes place in a clean room. Clean rooms have a rating system that ranges from Class 1 to Class 10,000. These particles are not visible to the naked eye and in an uncontrolled atmosphere, the workers must wear clean room suits that cover their body from head to toe and do not collect or carry any particles.

Polishing:Most prime grade silicon wafers go through 2-3 stages of polishing, using progressively finer slurries or polishing compounds. The polishing process occurs in two steps, which are stock removal and final chemical mechanical polish (CMP). Both processes use polishing pads and polishing slurry. The stock removal process removes a very thin layer of silicon and is necessary to produce a wafer surface that is damage-free. After polishing, the silicon wafers proceed to a final cleaning stage that uses a long series of clean baths. This process removes surface particles, trace metals, and residues. Oftentimes a backside scrub is done to remove even the smallest particles.

Packaging:Once the wafers complete the final cleaning step, engineers sort them by specification and inspect them under high intensity lights or laser-scanning systems. This detects unwanted particles or other defects that may have occurred during fabrication. All wafers that meet the proper specifications are packaged in cassettes and sealed with tape. The wafers ship in a vacuum-sealed plastic bag with an airtight foil outer bag. This ensures that no particles or moisture enters the cassette upon leaving the clean room.

 

PAM-XIAMEN can offer you technology and wafer support, for more information, please visit our website: https://www.powerwaywafer.com,

send us email at sales@powerwaywafer.com and powerwaymaterial@gmail.com

Quality is our first priority. PAM-XIAMEN has been ISO9001:2008, owns and shares four modern facories which can provide quite a big range of qualified products to meet different needs of our customers, and every order has to be handled through our rigorous quality system. Test report is provided for each shipment, and each wafer are warranty.Before 1990, we are stated owned condensed matter physics research center. In 1990, center launched Xiamen Powerway Advanced Material Co., Ltd (PAM-XIAMEN), now it is a leading manufacturer of compound semiconductor material in China.

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