AT91SAM9G25-CU 16K 400MHz ARM Embbedded MPU ATMEL

AT91SAM9G25-CU ARM-based Embbedded MPU ATMEL 16 Kbytes Data Cache 400MHz BGA217

• Core
• ARM926EJ-S™ ARM® Thumb® Processor running at up to 400 MHz 1.0V +/- 10%
• 16 Kbytes Data Cache, 16 Kbytes Instruction Cache, Memory Management Unit

• One 64-Kbyte internal ROM embedding bootstrap routine:
• Boot on NAND Flash, SDCard, DataFlash® or serial DataFlash. Programmable order.
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• One 32-Kbyte internal SRAM, single-cycle access at system speed
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• High Bandwidth Multi-port DDR2 Controller
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• 32-bit External Bus Interface supporting 4-bank and 8-bank DDR2/LPDDR, SDR/LPSDR, Static Memories

• MLC/SLC 8-bit NAND Controller, with up to 24-bit Programmable Multibit
• Error Correcting Code (PMECC)
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• System running at up to 133 MHz
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• Power-on Reset Cells, Reset Controller, Shut Down Controller, Periodic
• Interval Timer, Watchdog Timer and Real Time Clock
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• Boot Mode Select Option, Remap Command
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• Internal Low Power 32 kHz RC and Fast 12 MHz RC Oscillators
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• Selectable 32768 Hz Low-power Oscillator and 12 MHz Oscillator
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• One PLL for the system and one PLL at 480 MHz optimized for USB High Speed
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• Twelve 32-bit-layer AHB Bus Matrix for large Bandwidth transfers
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• Dual Peripheral Bridge with dedicated programmable clock for best performance
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• Two dual port 8-channel DMA Controllers
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• Advanced Interrupt Controller and Debug Unit
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• Two Programmable External Clock Signals
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• Low Power Mode
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• Shut Down Controller with four 32-bit Battery Backup Registers
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• Clock Generator and Power Management Controller
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• Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities
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• Peripherals
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• ITU-R BT. 601/656 Image Sensor Interface
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• USB Device High Speed, USB Host High Speed and USB Host Full Speed with dedicated On-Chip Transceiver
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• One 10/100 Mbps Ethernet MAC Controller
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• Two High Speed Memory Card Hosts
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• Two Master/Slave Serial Peripheral Interface
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• Two 3-channel 32-bit Timer/Counters
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• one Synchronous Serial Controller
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• One 4-channel 16-bit PWM Controller
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• Three Two-wire Interfaces
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• Four USARTs, two UARTs, one DBGU
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• One 12-channel 10-bit Analog-to-Digital Converter
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• Soft Modem
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• Write Protected Registers
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• I/O
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• Four 32-bit Parallel Input/Output Controllers
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• 105 Programmable I/O Lines Multiplexed with up to Three Peripheral I/Os
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• Input Change Interrupt Capability on Each I/O Line, optional Schmitt trigger input
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• Individually Programmable Open-drain, Pull-up and pull-down resistor, Synchronous Output
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• Packages
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• 217-ball BGA, pitch 0.8 mm
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• 247-ball TFBGA, pitch 0.5 mm
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• 247-ball VFBGA, pitch 0.5 mm