LMC662CM Programmable IC Chips CMOS Dual Operational Amplifier

LMC662 CMOS Dual Operational Amplifier

General Description

The LMC662 CMOS Dual operational amplifier is ideal for operation from a single supply. It operates from +5V to +15V and features rail-to-rail output swing in addition to an input common-mode range that includes ground. Performance limitations that have plagued CMOS amplifiers in the past are not a problem with this design. Input VOS, drift, and broadband noise as well as voltage gain into realistic loads (2 kΩ and 600Ω) are all equal to or better than widely accepted bipolar equivalents.

This chip is built with National’s advanced Double-Poly Silicon-Gate CMOS process. See the LMC660 datasheet for a Quad CMOS operational amplifier with these same features.

Features

• Rail-to-rail output swing
• Specified for 2 kΩ and 600Ω loads
• High voltage gain: 126 dB
• Low input offset voltage: 3 mV
• Low offset voltage drift: 1.3 µV/˚C

• Ultra low input bias current: 2 fA
• Input common-mode range includes V⁻
• Operating range from +5V to +15V supply
• ISS = 400 µA/amplifier; independent of V+

• Low distortion: 0.01% at 10 kHz
• Slew rate: 1.1 V/µs
• Available in extended temperature range (−40˚C to +125˚C); ideal for automotive applications
• Available to a Standard Military Drawing specification

Applications

• High-impedance buffer or preamplifier
• Precision current-to-voltage converter
• Long-term integrator
• Sample-and-hold circuit
• Peak detector
• Medical instrumentation
• Industrial controls
• Automotive sensors

Absolute Maximum Ratings (Note 3)

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.

Differential Input Voltage                                              ±Supply Voltage

Supply Voltage (V⁺ − V⁻ )                                                                16V

Output Short Circuit to V⁺                                                        (Note 12)

Output Short Circuit to V⁻                                                          (Note 1)

Lead Temperature (Soldering, 10 sec.)                                        260˚C

Storage Temp. Range                                                  −65˚C to +150˚C

Voltage at Input/Output Pins                              (V⁺ ) +0.3V, (V⁻ ) −0.3V

Current at Output Pin                                                                  ±18 mA

Current at Input Pin                                                                        ±5 mA

Current at Power Supply Pin                                                          35 mA

Power Dissipation                                                                        (Note 2)

Junction Temperature                                                                    150˚C

ESD Tolerance (Note 8)                                                                1000V

Operating Ratings(Note 3)

Temperature Range

  LMC662AMJ/883, LMC662AMD                              −55˚C ≤ TJ ≤ +125˚C

  LMC662AI                                                                  −40˚C ≤ TJ ≤ +85˚C

  LMC662C                                                                      0˚C ≤ TJ ≤ +70˚C

  LMC662E                                                                 −40˚C ≤ TJ ≤ +125˚C

Supply Voltage Range                                                         4.75V to 15.5V

Power Dissipation                                                                         (Note 10)

Thermal Resistance (θJA) (Note 11)

  8-Pin Ceramic DIP                                                                       100˚C/W

  8-Pin Molded DIP                                                                         101˚C/W

  8-Pin SO                                                                                      165˚C/W

  8-Pin Side Brazed Ceramic DIP                                                   100˚C/W

Note 1: Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature and/or multiple Op Amp shorts can result in exceeding the maximum allowed junction temperature of 150˚C. Output currents in excess of ±30 mA over long term may adversely affect reliability.

Note 2: The maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(max)–TA)/θJA.

Note 3: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed.

Note 4: Typical values represent the most likely parametric norm. Limits are guaranteed by testing or correlation.

Note 5: V+ = 15V, VCM = 7.5V and RL connected to 7.5V. For Sourcing tests, 7.5V ≤ VO ≤ 11.5V. For Sinking tests, 2.5V ≤ VO ≤ 7.5V.

Note 6: V+ = 15V. Connected as Voltage Follower with 10V step input. Number specified is the slower of the positive and negative slew rates.

Note 7: Input referred. V+ = 15V and RL = 10 kΩ connected to V+/2. Each amp excited in turn with 1 kHz to produce VO = 13 VPP.

Note 8: Human body model, 1.5 kΩ in series with 100 pF.

Note 9: A military RETS electrical test specification is available on request. At the time of printing, the LMC662AMJ/883 RETS spec complied fully with the boldface limits in this column. The LMC662AMJ/883 may also be procured to a Standard Military Drawing specification.

Note 10: For operating at elevated temperatures the device must be derated based on the thermal resistance θJA with PD = (TJ–TA)/θJA.

Note 11: All numbers apply for packages soldered directly into a PC board.

Note 12: Do not connect output to V+ when V+ is greater than 13V or reliability may be adversely affected

Connection Diagram

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