Active Member
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[China]
Address: Room 36B1-B2, Building C, Electronics Science & Technology Building Shennan Mid-Road, Shenzhen China
Contact name:Sharon Yang
Anterwell Technology Ltd. |
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Features
Features of the ADC module include:
• Linear successive approximation algorithm with 12 bits resolution.
• Up to 28 analog inputs.
• Output formatted in 12-, 10- or 8-bit right-justified format.
• Single or continuous conversion (automatic return to idle after single conversion).
• Configurable sample time and conversion speed/power.
• Conversion complete flag and interrupt.
• Input clock selectable from up to four sources.
• Operation in wait or stop3 modes for lower noise operation.
• Asynchronous clock source for lower noise operation.
• Selectable asynchronous hardware conversion trigger.
• Automatic compare with interrupt for less-than, or greater-than or equal-to, programmable value.
Compare Value High Register (ADCCVH)
In 12-bit mode, the ADCCVH register holds the upper four bits of the 12-bit compare value. These bits are compared to the upper four bits of the result following a conversion in 12-bit mode when the compare function is enabled
In 10-bit mode, the ADCCVH register holds the upper two bits of the 10-bit compare value (ADCV9 – ADCV8). These bits are compared to the upper two bits of the result following a conversion in 10-bit mode when the compare function is enabled. In 8-bit mode, ADCCVH is not used during compare.
Block Diagram
