Active Member
|
[China]
Address: Room 36B1-B2, Building C, Electronics Science & Technology Building Shennan Mid-Road, Shenzhen China
Contact name:Sharon Yang
Anterwell Technology Ltd. |
|
|
Features
• IMVP-IV™ Compliant CORE Regulator
• Single-Phase Power Conversion
• “Loss-less” Current Sensing for Improved Efficiency and Reduced Board Area
- Optional Discrete Precision Current Sense Resistor
• Internal Gate Drive and Boot-Strap Diode
• Precision CORE Voltage Regulatin
- 0.8% System Accuracy Over-temperature
• 6-Bit Microprocessor Voltage Identification Input
• Programmable “Droop” and CORE Voltage Slew Rate to Comply with IMVP-IV™ Specification
• Discontinuous Mode Of Operation for Increased Light Load Efficiency in Deep and Deeper Sleep Mode
• Direct Interface with System Logic
(STP_CPU and DPRSLPVR) for Deep and Deeper Sleep Modes of Operation
• Easily Programmable Voltage Setpoints for Initial “Boot”, Deep Sleep and Deeper Sleep Modes
Description
The ISL6218 Single-Phase Buck PWM control IC, with integrated half bridge gate driver, provides a precision voltage regulation system for advanced Pentium-M microprocessors in notebook computers. This control IC also features both input voltage feed-forward and average current mode control for excellent dynamic response, “Loss-less” current sensing using MOSFET rDS(ON), and user selectable switching frequencies from 250kHz to 500kHz per phase
The ISL6218 includes a 6-bit digital-to-analog converter (DAC) that dynamically adjusts the CORE PWM output voltage from 0.700V to 1.708V in 16mV steps, and conforms to the Intel IMVP-IV™ mobile VID specification. The ISL6218 also has logic inputs to select Active, Deep Sleep and Deeper Sleep modes of operation. A precision reference, remote sensing and proprietary architecture with integrated processor-mode compensated “Droop” provides excellent static and dynamic CORE voltage regulation.
Another feature of the ISL6218 IC controller is the internal PGOOD delay circuit that holds the PGOOD pin low for 3ms to 12ms after the VCCP and VCC_MCH regulators are within regulation. This PGOOD signal is masked during VID changes. Output overvoltage and undervoltage are monitored and result in the converter latching off and PGOOD signal being held low.
Ordering Information
| PART NUMBER | PART MARKING | TEMP. RANGE (°C) | PACKAGE | DWG # |
| ISL6218CV* | ISL 6218CV | -10 to +85 | 38 Ld TSSOP | M38.173 |
| ISL6218CVZ* (Note) | ISL 6218CVZ | -10 to +85 | 38 Ld TSSOP (Pb-free) | M38.173 |
| ISL6218CVZA* (Note) | ISL 6218CVZ | -10 to +85 | 38 Ld TSSOP (Pb-free) | M38.173 |
| ISL6218CRZ* (Note) | ISL62 18CRZ | -10 to +85 | 40 Ld 6x6 QFN (Pb-free) | L40.6x6 |
Absolute Maximum Ratings
Supply Voltage VDD, VDDP . . . . . . . . . . . . . . . . . . . . . . -0.3 to +7V
Battery Voltage, VBAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+25V
Boot1 and UGATE1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+33V
Phase1 and ISEN1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+28V
Boot1 with respect to Phase1 . . . . . . . . . . . . . . . . . . . . . . . . . +6.5V
UGATE1. . . . . . . . . . . . . . . . . . . . (Phase1 - 0.3V) to (Boot1 + 0.3V)
All other pins . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VDD + 0.3V)
Recommended Operating Conditions
Supply Voltage, VDD, VDDP . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%
Battery Voltage, VBAT . . . . . . . . . . . . . . . . . . . . . . . . . +5.6V to 21V
Ambient Temperature. . . . . . . . . . . . . . . . . . . . . . . . .-10°C to +85°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .-10°C to +125°C
